The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a semiconductor structure that includes a ferroelectric gate interconnect connecting underlying functional gate stacks of complementary metal oxide semiconductor (CMOS) transistors and a method of forming the same.
Ferroelectric field effect transistors (FETs) are attractive candidates for low power applications. FET structures coupling ferroelectric materials with the gate stacks of metal oxide semiconductor field effect transistors (MOSFETs) have been shown to demonstrate steep sub 60 mV/dec sub-threshold swing. However, no CMOS integration has been shown yet.
Moreover, to attain sufficient ferroelectric characteristics, the ferroelectric material film in a ferroelectric capacitor has to be relatively thick (on the order of 5 nm or greater). Using existing technology, integration of such a thick ferroelectric material film in a replacement gate process flow is challenging due to limited space for device formation and/or shorting of the ferroelectric capacitor. As such, there is a need for providing a method in which a ferroelectric capacitor can be readily integrated in a replacement gate process flow, while circumventing the space issue and/or shorting issue that hampers existing technology.